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| T108 Release Copyright by Terawins, Inc. Release Version 1.0 May 27, 2007 T108 Video Display Controller 1 www.fpdclub.net T108 Release Copyright by Terawins, Inc. Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction .................................................................................................................... 3 Features ................................................................................................................................................. 3 General Description ............................................................................................................................... 4 Applications............................................................................................................................................ 4 System Architecture............................................................................................................................... 5 System Configurations........................................................................................................................... 6 Pinout Diagram ...................................................................................................................................... 7 Pin Description ....................................................................................................................................... 8 2 2.1 2.2 2.3 2.4 2.5 2.6 Theory of Operations ................................................................................................... 11 IC Command Protocol ........................................................................................................................ 11 Analog Front End ................................................................................................................................. 13 Black-Level Extension (BLE) ............................................................................................................... 14 Color Space Converter ........................................................................................................................ 14 Gamma Correction............................................................................................................................... 15 OSD1 ................................................................................................................................................... 16 3 Register Description .................................................................................................... 37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 ADC Register Set................................................................................................................................. 37 Input Timing Register Set .................................................................................................................... 45 Picture Enhancement Register Set...................................................................................................... 51 Scaling Register Set ............................................................................................................................ 54 Gamma and Pattern Gen. Register Set............................................................................................... 58 OSD1 Register Set .............................................................................................................................. 60 LCD Output Control Register Set......................................................................................................... 60 Global Control Register Set ................................................................................................................. 67 TCON Register Set .............................................................................................................................. 73 Infra-Red Register Set ......................................................................................................................... 75 ITU - 656 Decoder Register Set........................................................................................................... 76 Y/C Separation and Chroma Decoder Register Set ............................................................................ 79 Digital I/O Pad Operation Condition..................................................................................................... 84 DC Characteristics ............................................................................................................................... 85 AC Characteristics ............................................................................................................................... 86 Analog Processing and A/D Converters .............................................................................................. 86 IC Host Interface Timing ..................................................................................................................... 87 4 4.1 4.2 4.3 4.4 4.5 Electrical Characteristics............................................................................................. 84 5 6 7 8 9 Package Dimensions ................................................................................................... 88 Ordering Information.................................................................................................... 88 Revisions Note ............................................................................................................. 89 General Disclaimer ....................................................................................................... 89 Contact Information ..................................................................................................... 89 2 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 1 Introduction 1.1 Features Cost Effective Highly Integrated Triple ADC + ITU656/601 Decoder + Digital RGB + 2D Video Decoder + OSD + Scaler + TCON + DAC + DCto-DC + LED/CCFL controls - Integrates 10-bit Triple Analog to Digital Converters (ADC) & Phase Locked Loop (PLL), for supporting CVBS, S-Video, YPbPr and RGB inputs - Scaler supports 2-D adaptive intra-field deinterlacer and non-linear 16:9 aspect ration. - Requires no external Frame Buffer Memory for de-interlace. - ITU656/601_8/L601_16 Decoder with digital input ports for standard ITU656/601 input data. - Support digital RGB565 inputs - Advanced On Screen Display (OSD) function - Programmable Timing Controller (Tcon) for Car TV applications - Multi-standard color decoder with 2D adaptive comb filter - Innovative and flexible design to reduce total system cost Triple 10-bits ADCs - 80MSPS Conversion Rate ADC - Built-in Pre-amp, mid-level & ground clamp - Automatic Clamp Control for CVBS, Y and C - Programmable Static Gain Control or Automatic Gain Control for CVBS or Y/C - Max Input configuration up to 9xCVBS, 3xSvideo+3xCVBS, 3YPbPr - Build-in Line-Lock PLL for RGB and YPbPr - Phases Tracking and Boundary for adjusting input quality. Digital Video Enhancement - Separate Luminance and Chroma Enhancer - Y Supports Luminance Black Level Extension., Contrast and Brightness adjustment - C Supports DCTI, Saturation and Hue adjustment. FIR Based Advanced Scaling Engine - Coefficient based sharpness filters - Independent vertical and horizontal scaling ratio - 16:9 Non-linear Aspect ratio LCD Interface Package: 100 pin LQFP Provides 256-entry TBL Gamma correction for panel compensation Supports image pan functions Programmable Timing Controller Built-in software adjustable VCOM voltage RGB Triple DAC output Integrated high efficiency DC-DC power conversion unit for gate and source drivers reduces energy consumption Integrated TFT-LCD backlight inverter drive unit supports CCFL/LED typed backlight Software adjustable lamp dimming - Built-in On Screen Display Engine - 8K-word OSD1 memory - Supports text or bitmap modes - Supports character blinking and overlay functions - Fully programmable character mapping - Supports alpha blending |
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